Payam Heydari

Assistant Professor, Electrical Engineering and Computer Science
The Henry Samueli School of Engineering

PH.D., University of Southern California

Phone: (949) 824-9324
Fax: (949) 824-3203

University of California, Irvine
Engineering Tower 644C
Irvine, CA 92697
Research Interests
Design of high-speed Analog, RF, and mixed-signal integrated circuits, and analysis of signal integrity and high-frequency effects of on-chip interconnects in high-speed VLSI circuits
Research Abstract
Ultra High-Speed CMOS Integrated Circuits for Optical Communication Networks

This research develops the design and analysis of ultra high-speed circuits in Complementary Metal Oxide Semiconductor (CMOS) technology for multi-gigabit Ethernet and optical time division multiplexed (OTDM) networks. We focus on the CMOS technology due to its low cost, high yield, and the relative ease of mixing analog and digital circuits on a large scale. We develop innovative techniques to design circuits that can operate at 20GHz, and thus, are suitable for future grades of SONET networks and multi-gigabit Ethernet. More precisely, a new and inexpensive all-electrical architecture of a low jitter phase-locked loop (PLL) clock recovery circuit that is capable of recovering up to 20GHz base rate clock from 100Gbit/sec OTDM networks is being developed. Next, a thorough study and analysis of the PLL jitter in the presence of external noise sources (e.g., P/G bounce and substrate noise) by using a stochastic modeling of these noise sources is performed. Finally, design of a low-noise microwave CMOS transimpedance amplifier for the front-end portion of the receiving section is undertaken.

Noise and Signal Integrity in High-Speed VLSI Circuits

Noise is a crucial problem in modern mixed-signal VLSI circuits and is becoming increasingly important as the minimum feature size shrinks to 0.13 micron and below. Noise sources are either internal to the devices (e.g., shot noise, 1/f noise, and thermal noise), or external sources (e.g. bounce noise, crosstalk noise, and charge sharing noise). Due to their higher magnitude and energy, the external noise sources play a more important role in determining the circuit reliability and performance.

Power/ground noise and crosstalk are major external noise sources that can have harmful effects on the circuit performance and reliability. For example, they can cause false switching in the logic gates especially dynamic logic gates, timing failures due to setup and hold time violations, and timing jitter in the on-chip clock generators. The goal of this research is to analysis power/ground noise and crosstalk in VLSI circuits. We further focus on the effect of power/ground noise on the timing jitter of CMOS phase lock loops (PLLs).

Model-Reduction of Very Large LTI Networks
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