Nader Bagherzadeh
Professor, Electrical Engineering and Computer Science
The Henry Samueli School of Engineering
The Henry Samueli School of Engineering
Chair
PH.D., The University of Texas at Austin
University of California, Irvine
EECS Dept.
Mail Code: 2625
Irvine, CA 92697
EECS Dept.
Mail Code: 2625
Irvine, CA 92697
Research Interests
Computer Architecture, Low Power Parallel DSP, Reconfigurable Computing, Computer Graphics, VLSI Design
Research Abstract
Reconfigurable DSP (RDSP)
PI: Nader Bagherzadeh
Funding: DARPA, NSF, CoRe/Broadcom
After the successful completion of the VLSI implementation and testing of our M1 chip that was based on the original Morpho architecture, the work has continued towards software development and architectural enhancements. The current work has resulted in developing efficient resource management algorithms for RDSP as well as extending the architecture to include new capabilities for computer graphics applications (e.g., ray tracing) as well as handling DVB-T (digital video broadcast DSP)baseband processing
Power Aware System Software and Algorithms
PI: Nader Bagherzadeh
Funding: DARPA
The power aware scheduling is an important component of many embedded systems such as mobile wireless systems and autonomous vehicles. All these systems have a common denominator: Power resources are limited and need to be spent efficiently and there are real-time tasks that need to be completed. My work in this area has resulted in a task scheduling software called IMPACCT that allows, in a user friendly manner, efficient scheduling of real-time tasks given the availability of a limited power resource. This approach for task scheduling is quite unique and has been proven successful when applied to the Mars Rover data obtained from NASA. If the IMPACCT tool was utilized for the Mars Rover mission, it would have reduced energy consumption by at least 20 percent, resulting in a longer mission on Mars. I have been working closely with Rockwell Collins to enhance and incorporate our tool for the next generation military radio systems called Joint Tactical Radio System (JTRS).
PI: Nader Bagherzadeh
Funding: DARPA, NSF, CoRe/Broadcom
After the successful completion of the VLSI implementation and testing of our M1 chip that was based on the original Morpho architecture, the work has continued towards software development and architectural enhancements. The current work has resulted in developing efficient resource management algorithms for RDSP as well as extending the architecture to include new capabilities for computer graphics applications (e.g., ray tracing) as well as handling DVB-T (digital video broadcast DSP)baseband processing
Power Aware System Software and Algorithms
PI: Nader Bagherzadeh
Funding: DARPA
The power aware scheduling is an important component of many embedded systems such as mobile wireless systems and autonomous vehicles. All these systems have a common denominator: Power resources are limited and need to be spent efficiently and there are real-time tasks that need to be completed. My work in this area has resulted in a task scheduling software called IMPACCT that allows, in a user friendly manner, efficient scheduling of real-time tasks given the availability of a limited power resource. This approach for task scheduling is quite unique and has been proven successful when applied to the Mars Rover data obtained from NASA. If the IMPACCT tool was utilized for the Mars Rover mission, it would have reduced energy consumption by at least 20 percent, resulting in a longer mission on Mars. I have been working closely with Rockwell Collins to enhance and incorporate our tool for the next generation military radio systems called Joint Tactical Radio System (JTRS).
Publications
A. Koohi, N. Bagherzadeh, and Chengzhi Pan, “A Fast Parallel-Solomon Decoder on a Reconfigurable Architecture,” IEEE/ACM CODES-ISSS 2003 Conference, Newport Beach , CA
M. Sanchez-Elez, H. Du, N. Tabrizi, Y. Lung, N. Bagherzadeh, and M. Fernandez, “Algorithm Optimizations and Mapping Scheme for Interactive Ray Tracing on a Reconfigurable Architecture,” Computers & Graphics, 2003
G. Venkataramani, W. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm and J. Hammes, “Automatic Compilation to a Coarse-grained Reconfigurable System-on-Chip,” ACM Trans. on Embedded Computing Systems, November 2003.
R. Maestre, F. Kurdahi, M. Fernandez, R. Hermida, N. Bagherzadeh, and H. Singh, “A Framework for Reconfigurable Computing: Task Scheduling and Context Management,” IEEE Transactions on VLSI Design-Special Issue on System Level Design, Vol. 9, Issue 6, pp. 858-873, Dec 2001 (Best Paper Award).
H. Singh, M. Lee, G. Lu, F. Kurdahi, N. Bagherzadeh, and E. Filho, “MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications,”IEEE Transactions on Computers, Vol. 49, No. 5, pp. 465-481 (2000).
S. Wallace and N. Bagherzadeh, “Modeled and measured instruction fetching performance for superscalar microprocessors,” IEEE Transactions on Parallel and Distributed Systems, Vol. 9, No. 6, (1998).
Professional Societies
IEEE, ACM
Link to this profile
https://faculty.uci.edu/profile/?facultyId=2324
https://faculty.uci.edu/profile/?facultyId=2324
Last updated
10/14/2004
10/14/2004