Alexandru Nicolau


Professor
Donald Bren School of Information and Computer Sciences
Professor, Electrical Engineering and Computer Science
The Henry Samueli School of Engineering

PH.D., Yale University

Phone: (949) 824-4079
Fax: (949) 824-4056
Email: anicolau@uci.edu

University of California, Irvine
204 IERF
Mail Code: 3425
Irvine, CA 92697
Research Interests
Parallel Computation, Architectures, Compilers, Programming Languages
URL
Research Abstract
Parallel programs, especially those with truly critical time (speed) requirements, are difficult to design. The process is extremely error-prone, tedious and time-consuming. The first goal of Dr. Nicolau's work is to design and implement a system of program transformations that support the semi-automatic (and eventually fully-automatic) exploitation of substantially all the parallelism available in a given program.


A second, and closely related, goal of Dr. Nicolau's work is to provide a tool for the rigorous study and development of parallelizing compilers. Furthermore, he is interested in precisely (formally) understanding and delimiting the power and limitations of such compilers. In particular, he studies the correctness and completeness (applicability) of parallelizing transformations, as well as comparing their relative power to expose/exploit parallelism. These issues are being examined within a unified formalism, which will allow him to make meaningful comparisons between transformations. This should lead to the design of new, more powerful and/or more general transformations. By designing his environment around this formal model and integrating the results of the theoretical work into his environment, he will have the means of empirically corroborating his formal results, and determining the usefulness of his transformaitons in the context of real code. In turn, this should yield a prototype integrated environment which will satisfy his first goal.


A third goal of this project is to investigate the relative trade-offs between run-time and compile-time parallelism exploitation. In particular, through Dr. Nicolau's formal and experimental tools he hopes to gain insight as to the proper balance between compile-time parallelization and run-time support, and the power of various architectural models in terms of their ability to exploit parallelism.


A final goal of Dr. Nicolau's work is to examine the relationship between parallel languages and parallelizing compilers. He believes that even when the ability to specify parallelism explicitly in the program at the user level is available, much can be done by the compiler to enhance the parallelism exposed, and to help avoid many errors that could otherwise be introduced by the user, and could be very time-consuming to identify without the system's help.
Publications
"Mutation Scheduling: A Unified Approach to Compiling for Fine-Grain Parallelism," (with S. Novack), Lecture Notes in Computer Science, Springer-Verlag, 1994.
 
"Optimal Register Assignment to Loops for Embedded Code Generation," (with D. Kolson, N. Dutt and K. Kennedy), ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 2, April 1996.
 
"Elimination of Redundant Memory Traffic in High-Level Synthesis," (with D. Kolson and N. Dutt), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 11, November 1996.
 
"Memory Organization for Improved Data Cache Performance in Embedded Processors," (with P. Panda and N. Dutt), Proceedings of the 1996 International Symposium on System Synthesis, November 1996.
 
"Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications," (with P. Panda and N. Dutt), Proceedings of the 1997 European Design and Test Conference (ED&TC 1997), March 1997.
Last updated
02/26/2002