Fadi J. Kurdahi

Associate Professor, Electrical Engineering and Computer Science
The Henry Samueli School of Engineering

PH.D., University of Southern California

Phone: (949) 824-8104
Fax: (949) 824-2321
Email: kurdahi@uci.edu

University of California, Irvine
516C Engineering Tower
Mail Code: 2625
Irvine, CA 92697

VLSI System Design and Design Automation of Digital Systems
URL www.eng.uci.edu/faculty/kurdahi/fadi.html
Evaluation Tools for the VLSI Design Process
Investigator: F.J. Kurdahi
Research Assistant: C. Ramachandran
Support: ACM/SIGDA
Cadence Design Systems
Center for High-Speed Image/Signal Processing
University of California MICRO Program

One of the most important challenges facing the semiconductor and computer industry lies in the capability of producing Application Specific Integrated Circuits (ASICs) with a quick turn-around cycle from the time the logic design is conceived to the time working chips are produced. As the various layout tasks involved in chip design take a long time and frequently must be repeated over again, providing the chip designer with the capability of quickly estimating the area and performance of the chip layout prior to laying it out will reduce greatly the number of iterations and therefore the design turn-around time. It is expected that if accurate evaluation tools are used throughout the design procedure, the resulting layouts will be faster and more compact in size.

System-Level Partitioning of VLSI Designs
Investigator: F.J. Kurdahi
Research Assistant: D. Rao
Support: Cadence Design Systems
Irvine Faculty Research Fellowship
University of California MICRO Program

The project is a study of the system-level partitioning problem in VLSI design, where large circuit designs are partitioned over several VLSI chips. One of the important tasks in this problem is the partitioning of the design to use as few chips as possible while still satisfying the overall constraints. The solutions being proposed make use of various design evaluation tools. Having a system-level partitioning tool coupled with design evaluation and estimation tools will enable the chip designer to estimate better the yield early in the design process and, therefore, have a fairly accurate assessment of the feasibility and cost of the system production. The tools being developed will be integrated under a spreadsheet-like environment.
Link to this profile http://www.faculty.uci.edu/profile.cfm?faculty_id=2590
Last updated 04/15/2002