Guann-Pyng Li
Professor, Electrical Engineering and Computer Science
The Henry Samueli School of Engineering
The Henry Samueli School of Engineering
PH.D., University of California, Los Angeles
University of California, Irvine
2200 EG
Mail Code: 2625
Irvine, CA 92697
2200 EG
Mail Code: 2625
Irvine, CA 92697
Research Interests
High-speed semiconductor technology, optoelectronic devices, integrated circuit fabrication and testing
Academic Distinctions
Appointments
Research Abstract
Analog Performance of BiCMOS Technology
Investigator: G.P. Li
Research Assistants: L. Chu, S. Martin, and J. Zhao
Support: AT&T Bell Laboratories
Hughes Aircraft
IBM
NCR Microelectronics Division
University of California MICRO Program
A BiCMOS technology is a process to fabricate highperformance vertical biopolar transistors, N- and P-channel MOSFETs on the same chip. BiCMOS processes promise lower power/high speed and the highest analog performance combined with complete digital functionality. The project is focused on the optimization of bipolar analog performance, including the development of a cut-off frequencey of 20 GHz in npn, noise and device matching in the polysilicon emitter transistors, and analog circuit reliability.
Emitter/Base Engineering in GaAs Heterojunction Bipolar Transistors
Investigator: G-P. Li
Research Assistants: Y. Chang and P. Chou
Support: Rockwell International Corporation
TRW
University of California MICRO Program
Heterojunction bipolar transistors (HBTs), which are formed by two different materials with a good crystal lattice match, emerge as one of the core technologies for implementing a variety of advanced microwave and millimeter wave communication systems. This research focuses on the concept, modeling, and realization of emitter/base engineering in HBTs for optimization of device speed and reliability. This includes (1) the dopant impurities and concentration in the base layer; (2) the design of heterojunction emitters; (3) the passivation of emitter/base surface layers; (4) the ideal ohmic contact formation; and (5) the high current density on device reliability.
Instability and Reliability in SOS/SOI MOSFETs
Investigator: G.P. Li
Research Assistants: E. Chao, C. Hu, and S. Martin
Support: Rockwell International
University of California MICRO Program
In the fabrication of field effect transistors, SOS/SOI technologies offer significant advantages such as simplified device isolation, reduced parasitic capacitances, improved radiation hardness in the space electronics, and the potential for three-dimension integration. This project is focused on device parameter characterization and design optimization for SOS/SOI MOSFETs with floating body operation. The key device design parameters will be identified to minimize the device instability induced by the parasitic bipolar action and to alleviate the hot carrier reliability concerns.
Low Frequency Noise in CMOS Technologies
Investigator: G.P. Li
Research Assistants: C. Hu and S. Martin
Support: Rockwell International
University of California MICRO Program
In reducing power supply voltage for low-power dissipation in the mixed analog/digital circuit design, the noise performance constraints imposed on analog circuits need to be evaluated. This project is focused on the development of a physics-based noise model for geometry scaled-down CMOSFETs and optimization of device noise performance for analog applications. The key device/process design parameters will be identified to minimize the 1/fà noise source induced by plasma etching conditions in wafer processing. Based on the noise model of submicron CMOSFETs, the design technique of low noise amplifiers will be examined.
Non-Invasive Probing in VLSI Technology
Investigator: G.P. Li
Research Assistant: Y. Hua
Support: IBM Research Initiation Award
Toshiba America Electronic Components, Inc.
As the device integration level increases and the fabrication process becomes more complicated in ULSI era, a non-invasive in-line diagnosis technique to monitor defects induced in wafer processing is essential to IC chips yield improvement. This project is focused on the development of such a technique, based on a second-harmonic generation effected by device fabrication processes. The additional information attained in the novel technique can further assist technologists in process design for device performance/yield enhancement.
Investigator: G.P. Li
Research Assistants: L. Chu, S. Martin, and J. Zhao
Support: AT&T Bell Laboratories
Hughes Aircraft
IBM
NCR Microelectronics Division
University of California MICRO Program
A BiCMOS technology is a process to fabricate highperformance vertical biopolar transistors, N- and P-channel MOSFETs on the same chip. BiCMOS processes promise lower power/high speed and the highest analog performance combined with complete digital functionality. The project is focused on the optimization of bipolar analog performance, including the development of a cut-off frequencey of 20 GHz in npn, noise and device matching in the polysilicon emitter transistors, and analog circuit reliability.
Emitter/Base Engineering in GaAs Heterojunction Bipolar Transistors
Investigator: G-P. Li
Research Assistants: Y. Chang and P. Chou
Support: Rockwell International Corporation
TRW
University of California MICRO Program
Heterojunction bipolar transistors (HBTs), which are formed by two different materials with a good crystal lattice match, emerge as one of the core technologies for implementing a variety of advanced microwave and millimeter wave communication systems. This research focuses on the concept, modeling, and realization of emitter/base engineering in HBTs for optimization of device speed and reliability. This includes (1) the dopant impurities and concentration in the base layer; (2) the design of heterojunction emitters; (3) the passivation of emitter/base surface layers; (4) the ideal ohmic contact formation; and (5) the high current density on device reliability.
Instability and Reliability in SOS/SOI MOSFETs
Investigator: G.P. Li
Research Assistants: E. Chao, C. Hu, and S. Martin
Support: Rockwell International
University of California MICRO Program
In the fabrication of field effect transistors, SOS/SOI technologies offer significant advantages such as simplified device isolation, reduced parasitic capacitances, improved radiation hardness in the space electronics, and the potential for three-dimension integration. This project is focused on device parameter characterization and design optimization for SOS/SOI MOSFETs with floating body operation. The key device design parameters will be identified to minimize the device instability induced by the parasitic bipolar action and to alleviate the hot carrier reliability concerns.
Low Frequency Noise in CMOS Technologies
Investigator: G.P. Li
Research Assistants: C. Hu and S. Martin
Support: Rockwell International
University of California MICRO Program
In reducing power supply voltage for low-power dissipation in the mixed analog/digital circuit design, the noise performance constraints imposed on analog circuits need to be evaluated. This project is focused on the development of a physics-based noise model for geometry scaled-down CMOSFETs and optimization of device noise performance for analog applications. The key device/process design parameters will be identified to minimize the 1/fà noise source induced by plasma etching conditions in wafer processing. Based on the noise model of submicron CMOSFETs, the design technique of low noise amplifiers will be examined.
Non-Invasive Probing in VLSI Technology
Investigator: G.P. Li
Research Assistant: Y. Hua
Support: IBM Research Initiation Award
Toshiba America Electronic Components, Inc.
As the device integration level increases and the fabrication process becomes more complicated in ULSI era, a non-invasive in-line diagnosis technique to monitor defects induced in wafer processing is essential to IC chips yield improvement. This project is focused on the development of such a technique, based on a second-harmonic generation effected by device fabrication processes. The additional information attained in the novel technique can further assist technologists in process design for device performance/yield enhancement.
Link to this profile
https://faculty.uci.edu/profile/?facultyId=2625
https://faculty.uci.edu/profile/?facultyId=2625
Last updated
03/29/2002
03/29/2002